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Cypress Semiconductor /psoc63 /CSD0 /STATUS

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Interpret as STATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CSD_SENSE)CSD_SENSE 0 (C_LT_VREF)HSCMP_OUT 0 (CSDCMP_OUT)CSDCMP_OUT

HSCMP_OUT=C_LT_VREF

Description

Status Register

Fields

CSD_SENSE

Only for Debug/test purpose this internal signal (sensor clock) status can be read by CPU
HSCMP_OUT

Only for Debug/test purpose the output status of CSD comparator can be read by CPU

0 (C_LT_VREF): N/A

1 (C_GT_VREF): N/A
CSDCMP_OUT

Only for Debug/test purpose the output status of CSD modulator can be read by CPU

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data